Abstract:
Next generation avionics Size Weight and Power (SWaP) can benefit from transformational improvements and flexibility in processing brought on by Moore's Law with proper heterogeneous pooled processor solutions. It is no longer feasible to simply use a modest number of network-connected single-core processors in isolated subsystems; instead, multicore processing is the norm. By 2016-2018, there will be on-chip multicore processors with 16 or more cores on each die integrated with on-chip transformational multi-Teraflop General Purpose Graphics Processing Units (GPGPUs). Heterogeneous reprogrammable System-on-Chip (SoC) devices will include multicore processors mixed with 5 billion transistor Field Programmable Gate Arrays (FPGAs). At this time, many avionics subsystems are just beginning the integration of multicore into safe and secure systems. Similarly, sensor critical avionics systems are still adjusting their heterogeneous processing mix in multicore, FPGA, and GPGPU processing solutions. Pooled processing across subsystems is still very limited in deployment. Subsystem level partitioning and security/safety considerations often still limit the potential SWAP improvement for pooled processing if not properly planned and managed. Legacy software migration also continues to make pooled processing in tech refresh a challenge. This paper presents results of an initial investigation into relevant dual use parallels from adjacent markets with similar challenges. One of the adjacent markets that can be used for open discussion of the heterogeneous pooled processor challenge is the driverless car processor architecture. There are already developments with Teraflop computing in the glove compartment, modular multi-sensor data fusion sensor software, integrated information and infrastructure hardware security, and standards for on-platform/off-platform cloud integration. Future cars will have hardware that runs up to 100 Million lines of code. What can the avionics industry leverage from this adjacent market as it moves forward in hybrid pooled processor architectures?